ASML：DRAM技术转变带来的光刻机收入增长

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30 September 2025

Global Semiconductors

ASML: Lithography headwinds from DRAM technology shifts

David Dai, CFA

+852 2918 5704

david.dai@bernsteinsg.com

Mark Li

+852 2123 2645

mark.li@bernsteinsg.com

Carmine Milano

+44 207 762 1857

carmine.milano@bernsteinsg.com

Juho Hwang

+852 2123 2632

juho.hwang@bernsteinsg.com

Edward Hou, CFA

+852 2123 2623

edward.hou@bernsteinsg.com

Yipin Cai, CFA

+852 2123 2669

yipin.cai@bernsteinsg.com

We believe the DRAM industry is facing a technology migration to 3D, first with the

transistor going to 3D / vertical structure, followed by full 3D DRAM stacking. This will

present a significant headwind to EUV intensity in DRAM vs. the current growth trend.

Migration to 4F2 likely to reduce DRAM scale while INCREASING feature size and

hence decreasing EUV intensity. In the past, increasing bit density in DRAM has been

about shrinking feature size (F). Since the D1a node, shrinking means increased use and

hence cost of EUV litho, which is getting too expensive. DRAM makers are thus weighing

the migration from the current 6F2 to 4F2. By placing transistors in DRAM cells vertically,

the 4F2 structure reduces the DRAM cell area by around 30%, and can thus afford to

increase the feature size. ASMI data shows 4F2 adoption is likely to step DRAM feature

size by 1-2 generations, back to 11nm. The impact: TEL shows EUV layer count can be cut

by half with 4F2; SK hynix said migration can potentially reduce the EUV costs to half of

that associated with 6F2. We expect 4F2 migration to happen ~2028, resulting in stagnant

DRAM EUV shipment, even with mild assumptions in EUV layer decrease.

Future migration to 3D DRAM may eliminate the use of EUV. The migration to 4F2

temporarily resets the feature size and hence EUV cost, but further shrinking will still result

in smaller features and higher EUV cost. The ultimate solution is 3D DRAM. By turning

the memory cells 90 degrees and then stacking them vertically, DRAM bit density can be

increased by increasing the number of layers instead of shrinking, akin to 3D NAND. As

such, the feature size can be reset back to 20-25nm according to Yole, which potentially

eliminates the need of EUV. China has a strong incentive to develop 3D DRAM given the

restriction of EUV imports. Although this is a challenging transition and is unlikely to happen

before early 2030s, it is a LT threat that cannot be ignored by long term investors. We

estimate that DRAM contributes 35-40% of the total EUV shipment in the next 5 years, and

if it’s no longer needed the damage is significant.

Recent developments are positive on ASML but we are conservative on the LT.

Samsung orders from Tesla, Intel getting investments, strong AI demand, and SK hynix

getting high NA machines are all positive to ASML for 1-2 years. However, we remain

conservative on the LT, given the DRAM 3D migration, logic EUV intensity, and China risk.

Our latest EUV model (EUV Model) shows its growth slowdown towards 2030, partially

due to the DRAM transition. ASML is no longer cheap at 33x P/E. Conversely, the 3D

migration is positive for advanced packaging (it employs CBA wafer to wafer stacking

and benefits DISCO/TEL) and etching/deposition (for making the 3D structure and

benefits TEL/Kokusai and ASMI (not covered).

For Samsung, hynix and Micron, the oligopolistic structure and supply discipline will

ensure they get the benefit of AI & data economy from now to early 2030s as the lack

of EUV prevents China from becoming an effective competitor. Beyond that 3D DRAM will

reduce the importance of EUV, but these companies have been researching 3D DRAM for

years, as evidenced in the patents filed a long time ago, and with an earlier start likely will

still be more competitive than China beyond early 2030s.

See the Disclosure Appendix of this report for required disclosures, analyst certifications and other

important information. Alternatively, visit our Global Research Disclosure Website.

www.bernsteinresearch.com

First Published: 29 Sep 2025 20:30 UTCCompletion Date: 29 Sep 2025 18:14 UTC

2025年9月30日

全球半导体

阿斯麦：DRAM技术转变带来的光刻挑战

戴维・戴，特许金融分析师

+852 2918 5704

david.dai@bernsteinsg.com

MarkLi

+852 2123 2645

mark.li@bernsteinsg.com

CarmineMilano

+44 207 762 1857

carmine.milano@伯恩斯坦sg.com

JuhoHwang

+852 2123 2632

juho.hwang@bernsteinsg.com

EdwardHou,特许金融分析师

ward.hou@bernsteinsg.com

蔡一平,CFA+852 2123 2669

pin.cai@bernsteinsg.com

我们相信，动态随机存取存储器行业正在面临向三维的技术迁移，首先晶体管将迁移到三

维/垂直结构，随后是完整的3DDRAM堆叠。这将给动态随机存取存储器的极紫外光刻强

度带来显著的逆风，与当前的增长趋势相比。

迁移到4F2 可能会减少动态随机存取存储器的规模，同时增加特征尺寸，从而降低极

紫外光刻强度。在过去，动态随机存取存储器中增加比特密度一直是通过缩小特征尺

寸（F）来实现的。自D1a节点以来，缩小意味着极紫外光刻的使用和成本增加，这变

得过于昂贵。因此，动态随机存取存储器制造商正在权衡从当前的6F2 迁移到4F2。通

过将晶体管垂直放置在动态随机存取存储器单元中，4F2 结构将动态随机存取存储器

单元面积减少约30%，因此可以增加特征尺寸。美国半导体行业协会的数据显示，

4F2 的采用可能会将动态随机存取存储器的特征尺寸提升1‑2代，回到11纳米。影响：

东京电子显示，使用4F2可以将极紫外光刻层数减半；SK海力士表示，迁移可以将极

紫外光刻成本降低到6F2的一半。我们预计4F2 迁移将在~2028发生，导致动态随机存

取存储器的极紫外光刻出货量停滞，即使极紫外光刻层数减少的假设较为温和。

未来迁移至3DDRAM可能消除对EUV的使用。迁移至4F2暂时重置了特征尺寸，因此也

重置了EUV成本，但进一步缩小仍会导致特征尺寸更小且EUV成本更高。最终解决方案

是3DDRAM。通过将存储单元旋转90度然后垂直堆叠，DRAM比特密度可以通过增加

层数而不是缩小来提高，类似于3DNAND。因此，根据Yole的说法，特征尺寸可以重

置回20‑25nm，这有可能消除对EUV的需求。鉴于EUV进口的限制，中国有强烈的动机

开发3DDRAM。尽管这是一个具有挑战性的过渡，并且不太可能在2030年代初之前发

生，但它是一个长期投资者不能忽视的LT威胁。我们估计DRAM在未来5年内占EUV总

出货量的35‑40%，如果不再需要，损失将是巨大的。

ASML的最新发展态势积极，但我们对长期前景持谨慎态度。来自特斯拉、英特尔的

投资订单，强劲的人工智能需求，以及SK海力士获得的高NA设备，都对ASML在1‑2

年内有利。然而，考虑到动态随机存取存储器（DRAM）的三维迁移、逻辑极紫外光

刻（EUV）强度以及中国风险，我们仍对长期前景持谨慎态度。我们的最新EUV模型

（EUV模型）显示其增长速度在2030年放缓，部分原因是DRAM的迁移。ASML的市

盈率（P/E）已达33倍，已不再便宜。相反，三维迁移对先进封装（它采用CBA晶圆

到晶圆堆叠，并受益于DISCO/东京电子）以及蚀刻/沉积（用于制造三维结构，并受

益于东京电子/国策和美利坚半导体行业协会（ASMI）（未覆盖））是积极的。

对于三星、海力士和美光来说，寡头垄断结构和供应纪律将确保它们从现在到2030年

代初都能从人工智能与数据经济中获益，因为缺乏极紫外光刻技术阻止了中国成为有

效竞争者。在那之后，3DDRAM将降低极紫外光刻技术的重要性，但这些公司多年来

一直在研究3DDRAM，这一点体现在很久以前提交的专利中，并且由于起步更早，它

们在2030年代初之后可能仍然比中国更具竞争力。

请参阅本报告的披露附录，以获取所需的披露信息、分析师认证和其他重要信息。或者，请访问我们的全球研究披

露网站。

www.bernsteinresearch.com

首次发布：2025年9月29日20:30UTC完成日期：2025年9月29日18:14UTC

David Dai, CFA  +852 2918 5704 david.dai@bernsteinsg.com 30 September 2025

BERNSTEIN TICKER TABLE

26 Sep

2025

TTM Reported EPS Reported P/E (x)

Closing Price Rel.

Ticker Rating Cur Price Target Perf. Cur 2024A 2025E 2026E 2024A 2025E 2026E

ASML M USD 951.52 743.00 (1.0)% USD 20.83 26.17 26.49 38.9 31.0 30.6

ASML.NA M EUR 825.50 640.00 (2.8)% EUR 19.24 24.17 24.48 42.9 34.2 33.7

005930.KS (SEC) O KRW 84,200 95,000 23.5% KRW 4,948.97 4,686.49 8,080.39 17.0 18.0 10.4

005935.KS (SEC-Pref) O KRW 66,500 80,750 17.2% KRW 4,948.97 4,686.49 8,080.39 13.4 14.2 8.2

SMSN.LI O USD 1,496.00 1,734.00 8.2% USD 90.66 83.78 147.45 16.5 17.9 10.1

000660.KS (SK hynix) O KRW 349,000 400,000 86.5% KRW 28,300 50,488 64,734 12.3 6.9 5.4

MU O USD 157.27 170.00 30.2% USD 1.26 8.14 14.64 124.5 19.3 10.7

8035.JP (Tokyo Electron) O JPY 26,505 29,400 (11.8)% JPY 1,179.08 1,057.50 1,262.81 22.5 25.1 21.0

6146.JP (DISCO) O JPY 46,810 52,800 8.2% JPY 1,119.74 1,153.84 1,389.59 41.8 40.6 33.7

SPX 6,661.21

EDM 1,493.07

ASIAX 1,575.97

EM 1,479.06

JPL 2,006.25

O - Outperform, M - Market-Perform, U - Underperform, NR - Not Rated, CS - Coverage Suspended

MU estimate is Adjusted EPS; MU valuation is Adjusted P/E (x);

Source: Bloomberg, Bernstein estimates and analysis.

INVESTMENT IMPLICATIONS

ASML (Market-Perform, EUR 640.00): We rate ASML Market-Perfom with PT of EUR 640

Samsung (Outperform, KRW 95,000): We rate Samsung Outperfom with PT of KRW 95,000

SK Hynix (Outperform, KRW 400,000): We rate SK Hynix Outperfom with PT of KRW 400,000

Micron (Outperform, USD 170): We rate Micron Outperform with target price of US$170.

Disco (Outperform, JPY 52,800): We rate Disco Outperform with target price of JPY 52,800.

Tokyo Electron (Outperform, JPY 29,400): We rate Disco Outperform with target price of JPY 29,400.

GLOBAL SEMICONDUCTORS 2

戴维・戴,特许金融分析师+852 2918 5704 david.dai@bernsteinsg.com 2025年9月30日

伯恩斯坦股票表

9月26日

2025

TTM 报告每股收益报告市盈率（倍）

关闭价格 Rel.

股票代码评级 Cur 价格目标表现 Cur 2024年 2025年预期 2026年预期 2024年 2025年预期 2026年预期

ASML M USD 951.52 743.00 (1.0)% USD 20.83 26.17 26.49 38.9 31.0 30.6

ASML.NA M EUR 825.50 640.00 (2.8)% EUR 19.24 24.17 24.48 42.9 34.2 33.7

005930.KS(SEC) O KRW 84,200 95,000 23.5% 韩元4,948.974,686.498,080.39 17.0 18.0 10.4

005935.KS(优先股) O KRW 66,500 80,750 17.2% 韩元4,948.974,686.498,080.39 13.4 14.2 8.2

SMSN.LI O USD 1,496.00 1,734.00 8.2% USD 90.66 83.78147.45 16.5 17.9 10.1

000660.KS(SK海力士) O KRW 349,000 400,000 86.5% KRW 28,300 50,48864,734 12.3 6.9 5.4

MU O USD 157.27 170.00 30.2% USD 1.26 8.14 14.64 124.5 19.3 10.7

8035.JP(东京电子) O JPY 26,505 29,400 (11.8)% 日元1,179.081,057.501,262.81 22.5 25.1 21.0

6146.JP(DISCO) O JPY 46,810 52,800 8.2% 日元1,119.741,153.841,389.59 41.8 40.6 33.7

SPX 6,661.21

EDM 1,493.07

亚细亚指数 1,575.97

EM 1,479.06

JPL 2,006.25

O‑跑赢，M‑市场表现，U‑跑输，NR‑未评级，CS‑覆盖暂停MU估计是调整后每股收益；

MU估值是调整后市盈率(x)；来源：彭博，伯恩斯坦估计和分析。

投资影响

ASML(市场表现,欧元640.00):我们给ASML市场表现评级为欧元640

三星(跑赢,韩元95,000):我们给予三星跑赢评级，目标价格为韩元95,000

SK海力士(跑赢,韩元400,000):我们给予SK海力士跑赢评级，目标价格为韩元400,000

美光(跑赢,美元170):我们给予美光跑赢评级，目标价格为美元170。

DISCO(跑赢,日元52,800):我们给予DISCO跑赢评级，目标价格为日元52,800。

东京电子(超额表现,日元29,400):我们给予DISCO超额表现评级，目标价格为日元29,400。

全球半导体 2

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David Dai, CFA  +852 2918 5704 david.dai@bernsteinsg.com 30 September 2025

DETAILS

EXECUTIVE SUMMARY

We expect EUV Intensity in DRAM manufacturing to reach a peak around 2027/28 with the HVM of the 1d node, after

which it will begin to decline with the transition to 4F2. Longer term, EUV intensity is likely to further fall sharply as

the industry moves to 3D DRAM next decade.

Over the past twenty years, increases in bit density in DRAM have been achieved by shrinking feature sizes, with each new node

requiring greater lithography intensity. With the transition to the 1a node in 2022, memory manufacturers were compelled to

adopt EUV tools to further reduce feature sizes, and each subsequent node has required a higher number of EUV exposures. We

believe that, for the next two to three years, DRAM density will continue to increase primarily through feature size reduction. EUV

intensity is expected to peak at the 1d node, where we estimate seven to eight EUV layers per wafer.

EUV tools are extremely costly, and the increasing number of tools required has placed a significant burden on memory

manufacturers, where controlling production costs is especially critical compared to logic. As a result, memory players are

planning to shift cell architecture rather than continue pushing planar scaling, aiming to reduce reliance on EUV. Similar to

the move from 8F2 to 6F2 cell design that occurred around 2004, the architectural change from 6F2 to 4F2 will enhance

performance without requiring further reductions in feature size (F). We anticipate 4F² DRAM to enter early production around

2028 at the D0a node. EUV shipments to DRAM manufacturers are expected to grow from ~15 in 2025 to ~30 by 2028, but

will level off by decade’s end. Despite rising DRAM capacity driven by HBM demand, fewer EUV exposures per wafer will keep

overall EUV demand stable. (Exhibit 1).

With 4F², DRAM makers are moving to vertical transistor architectures: Samsung calls this the Vertical Channel Transistor (VCT),

while SK hynix refers to it as Vertical Gate (VG). By putting transistor vertically below/above capacitor, the cell footprint shrinks

by about 30%, delivering improved bit density and power efficiency without requiring smaller lithographic features. Because

density gains no longer come from finer patterns, the number of EUV exposures can be reduced, cutting process cost and

complexity. SK hynix has indicated that with 4F², EUV costs could fall by as much as 50%. After the resetting, EUV exposures

will gradually go up again in subsequent 4F² nodes, but it’s set back by 1-2 generations.

Looking further out, beyond 2030, DRAM is widely expected to follow NAND’s path into true 3D stacking, where multiple layers

of cells are stacked vertically. In this architecture, density can scale by adding layers instead of shrinking features, dramatically

reducing or even eliminating the need for EUV lithography. While this remains in early development, the direction of travel is

clear: the burden of scaling is moving away from lithography and toward materials engineering processes such as etching,

deposition, and bonding.

In summary, DRAM scaling is moving through three phases: first, an EUV-intensive planar scaling phase culminating in the 1d

node; second, a transition to 4F² architecture that reduces EUV exposures and costs, before it gradually goes up again; and

finally, a longer-term move into 3D DRAM, which would allow bit density to scale dramatically without requiring more EUV layers

— or potentially eliminating the need for EUV altogether (Exhibit 2, Exhibit 3).

GLOBAL SEMICONDUCTORS 3

戴维・戴,特许金融分析师+852 2918 5704 david.dai@bernsteinsg.com 2025年9月30日

详情

执行摘要

我们预计，随着1d节点的HVM，DRAM制造中的EUV强度将在2027/28年左右达到峰值，之后随着向4F2的过渡将

开始下降。从长期来看，随着行业在下一个十年转向3DDRAM，EUV强度可能会进一步急剧下降。

在过去二十年间，动态随机存取存储器（DRAM）的比特密度通过缩小特征尺寸来实现提升，每个新节点都需要更高的光

刻强度。随着在2022年过渡到1a节点，内存制造商被迫采用极紫外光刻（EUV）设备以进一步缩小特征尺寸，而每个后

续节点都需要更多的EUV曝光。我们认为，在未来两到三年内，DRAM密度将主要通过特征尺寸缩小来提升。EUV强度预

计在1d节点达到峰值，我们估计每晶圆需要七到八个EUV层。

EUV设备成本极高，所需设备数量的增加给内存制造商带来了巨大负担，而与逻辑相比，控制生产成本尤为重要。因此，

内存制造商计划改变单元架构，而不是继续推动平面缩放，以减少对EUV的依赖。类似于2004年左右从8F2 到6F2 单元

设计的转变，从6F2 到4F2 的架构变化将在不进一步缩小特征尺寸（F）的情况下提升性能。我们预计4F2DRAM将在

2028年左右在D0a节点进入早期生产。预计EUV设备出货量到2028年将从2025年的~15 增长到~30 ，但在十年末趋于

平稳。尽管由HBM需求驱动的DRAM容量上升，但每晶圆EUV曝光次数减少将使整体EUV需求保持稳定。（图1）。

借助4F2，动态随机存取存储器制造商正转向垂直晶体管架构：三星称其为垂直沟道晶体管（VCT），而SK海力士则称其

为垂直栅极（VG）。通过将晶体管垂直地置于电容器下方/上方，单元面积可缩小约30%，从而在不需要更小的光刻特征

的情况下提高比特密度和电源效率。由于密度提升不再来自更精细的图案，因此可以减少EUV曝光次数，降低工艺成本

和复杂性。SK海力士已表示，借助4F2，EUV成本可能下降高达50%。在重置后，随后的4F2节点中EUV曝光次数将再次

逐渐上升，但会延迟1‑2代。

展望更长远的时间，在2030年之外，动态随机存取存储器预计将跟随NAND的路径进入真正的三维堆叠，其中多层单元

将垂直堆叠。在这种架构中，可以通过增加层数来提升密度，而不是缩小特征，从而大幅减少甚至消除对极紫外光刻的

需求。虽然这仍处于早期开发阶段，但发展方向明确：扩展的负担正从光刻转向材料工程工艺，如蚀刻、沉积和键合。

总而言之，DRAM缩放正经历三个阶段：首先，一个以EUV密集型平面缩放阶段，最终达到1d节点；其次，过渡到4F2架

构，减少EUV曝光次数和成本，然后逐渐再次上升；最后，进入一个更长期的3DDRAM阶段，这将允许比特密度大幅缩

放，而无需更多EUV层——或者可能完全消除对EUV的需求（图2，图3）。

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ASML：DRAM技术转变带来的光刻机收入增长

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